Conventional integrated circuit (IC) design methods utilize “hardware-based” approaches to predict device metrics (such as transistor performance metrics). For example, performance data can be collected from various dies on a number of fabricated wafers and then analyzed. Based on such analysis, models (e.g., transistor models) can then be created, which can serve as basis for simulating circuit behavior.
Such conventional approaches can suffice for mature fabrication processes. However, for processes still under development, such hardware data is generally unreliable as fabrication steps can be subject to change or the fabrication process drifts, making the initial metrics inaccurate thereby necessitating multiple rounds of design as the circuit behaviors evolve with the progression of the process development. Also, conventional approaches may only present performance data, making it difficult to obtain comprehensive information on how the sources of particular process variations can impact different device metrics.
Fabricated IC devices tend to encounter failures or underperforming components due to fabrication process variations, for instance, variations in threshold voltage. As a result, designers may elect to design conservatively, that is, to a wider set of process corners for the sake of ensuring a robust design but then sacrificing certain design targets. As semiconductor process advances to support Moore's law, the challenges of designing ICs in the context of process development only increase as the processes become more complex and therefore difficult to develop and implement. Design compensations for the ever-widening corners only increase. The trend continues with putting more and more burdens on design teams to tape out new chip products with satisfactory designs and meeting timelines for customers.